Load "C:\\Projects\\keil\\FM33ADisp\\test.axf"
* JLink Info: Device "CORTEX-M0" selected.
Set JLink Project File to "C:\Projects\keil\FM33ADisp\JLinkSettings.ini"
* JLink Info: Device "CORTEX-M0" selected.
 
JLink info:
----------
DLL: V7.82 , compiled Oct 13 2022 13:32:51
Firmware: J-Link V11 compiled Apr  1 2025 10:02:30
Hardware: V11.00
S/N : 603000869
Feature(s) : RDI, FlashBP, FlashDL, JFlash, GDB
 
* JLink Info: Found SW-DP with ID 0x0BB11477
* JLink Info: DPIDR: 0x0BB11477
* JLink Info: CoreSight SoC-400 or earlier
* JLink Info: Scanning AP map to find all available APs
* JLink Info: AP[1]: Stopped AP scan as end of AP map has been reached
* JLink Info: AP[0]: AHB-AP (IDR: 0x04770021)
* JLink Info: Iterating through AP map to find AHB-AP to use
* JLink Info: AP[0]: Core found
* JLink Info: AP[0]: AHB-AP ROM base: 0xE00FF000
* JLink Info: CPUID register: 0x410CC300. Implementer code: 0x41 (ARM)
* JLink Info: Unknown core, assuming Cortex-M0
* JLink Info: Found Cortex-M0 r0p0, Little endian.
* JLink Info: FPUnit: 4 code (BP) slots and 0 literal slots
* JLink Info: CoreSight components:
* JLink Info: ROMTbl[0] @ E00FF000
* JLink Info: [0][0]: E000E000 CID B105E00D PID 000BB00D ???
* JLink Info: [0][1]: E0001000 CID B105E00D PID 000BB00A DWT
* JLink Info: [0][2]: E0002000 CID B105E00D PID 000BB00B FPB
ROMTableAddr = 0xE00FF000
* JLink Info: Reset: Halt core after reset via DEMCR.VC_CORERESET.
* JLink Info: Reset: Reset device via AIRCR.SYSRESETREQ.
 
Target info:
----------
Device: FM33A04XEV
VTarget = 3.348V
State of Pins:
TCK: 1, TDI: 1, TDO: 0, TMS: 1, TRES: 1, TRST: 1
Hardware-Breakpoints: 4
Software-Breakpoints: 8192
Watchpoints:          1
JTAG speed: 5 kHz
 
Full Chip Erase Done.
Programming Done.
Verify OK.
* JLink Info: Reset: Halt core after reset via DEMCR.VC_CORERESET.
* JLink Info: Reset: Reset device via AIRCR.SYSRESETREQ.
Application running ...
Flash Load finished at 16:20:03

#include "init.h"
#include <stdint.h>
//#pragma GCC diagnostic ignored "-Wgnu-binary-literal"

void INIT(void){
   rcc();
   gpio();
   
}

void rcc(void){
   CMU->RCHFCR |= (0x1U << 8); // 16MHz
   CMU->RCHFCR |= 0x1U; // RCHF enable
   for(uint8_t i = 0; i < 255; i++);
   CMU->SYSCLKCR &=~ 0x7U; // SysClk -- RCHF
   //GPIO->FOUTSEL |= 0xBU; //Fout0 (PG6)
}

void gpio(void){
    //--- PORTG ---//
   //GPIOG->FCR |= (0x2U << 12); // PG6 -- digital function
   //GPIOG->DFS |= (0x1U << 6); // Fout
   GPIOG->PUEN |= (1 << 6);
   GPIOG->FCR |= (0x01U << 12);
   GPIOG->DSET |= (1 << 6);
   
}