void DS18_pinsetup(){
    TIM1->CR1 = 0;
    RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_AFIOEN;
    RCC->AHBENR |= RCC_AHBENR_DMA1EN;
    pin_set(GPIOA, 1<<8); // 1 @ line
    // PA8 as opendrain output
    GPIOA->CRH = (GPIOA->CRH & ~(GPIO_CRH_MODE8 | GPIO_CRH_CNF8)) |
            CRH(8, CNF_ODOUTPUT | MODE_FAST);
    TIM1->PSC = 71; // 1MHz
    // CC1 is output (PWM mode 1, active->inactive, enable preload), CC2 is input @TI1
    TIM1->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE |
            TIM_CCMR1_CC2S_1;
    // enable CC1 & CC2, CC1 active low
    TIM1->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC1P;
    TIM1->DIER = 0; // disable IRQ & DMA events
    // main output enable
    TIM1->BDTR = TIM_BDTR_MOE;
    // T1Ch2: per->mem, T1Ch1: mem->per; 16bit->8bit,
    DMA1_Channel2->CCR = DMA_CCR_MINC | DMA_CCR_PSIZE_0 | DMA_CCR_TCIE | DMA_CCR_DIR;
    DMA1_Channel3->CCR = DMA_CCR_MINC | DMA_CCR_PSIZE_0 | DMA_CCR_TCIE;
    DMA1_Channel2->CPAR = (uint32_t)&TIM1->CCR1;
    DMA1_Channel3->CPAR = (uint32_t)&TIM1->CCR2;
    TIM1->CR1 = TIM_CR1_URS; // only ARR overflow generates interrupt

    NVIC_EnableIRQ(TIM1_UP_IRQn); // last interrupt to turn timer off
    NVIC_EnableIRQ(DMA1_Channel2_IRQn);
    dsstate = DS18_SLEEP;
}

        case DS18_DETDONE:
            if(TIM1->CCR2 > RESET_BARRIER) DS18_startmeas(Tms);
            else dsstate = DS18_ERROR;
        break;